This invention relates to gallium arsenide (GaAs) field-effect transistors (FETs) and to methods of making such transistors. More particularly, this invention is concerned with a method for making self-aligned gate (SAG) GaAs transistors for use in the integrated circuit field.
Certain of the processing steps described in this application are included in a copending application entitled "A method of Making Self-Aligned GaAs Digital Integrated Circuits" filed on Oct. 21, 1985 as Ser. No. 789,523, now abandoned, for R. A. Sadler and A. E. Geissenberger 1-2.
The processes currently being used fall into two categories: (1) Thermally-Stable Refractory Gate (RG), and (2) Substantial Gate (GS). From a processing standpoint, the RG process is simpler and easier to manufacture than the SG process, but it places stringent requirements on the thermal stability of the Schottky gate metallization. The SG approach places no unusual thermal stability requirements on the gate metal but does require the difficult formation of a tri-layer gate substitution mask with a carefully controlled T-shaped profile.
While the RG approach may be superior overall to the SG approach, previous embodiments of the RG approach have suffered from the need to compromise some aspects of the process due to inadequate technology. In the SG process, gold is used as the refractory metal since it exhibits low resistivity and its thermal stability is sufficient for that process. However, in the RC process, the refractory metals used must be such that they can achieve the necessary thermal stability of the gate Schottky contact. Gold is not a suitable metal for this process. A major problem in the past has been the high resistivity of the refractory metals suitable for the RG process relative to that of gold. The high resistivity of the refractory gate metallization complicates the RG approach in that the first level interconnect metal, which must have lower resistivity than possible with a refractory metal, is defined by an additional mask level rather than the gate mask level as in the SG process. Also the high gate resistance degrades the performance of RG processed FETs, which precludes using this highly manufacturable process to fabricate analog circuits.